Pipelining and latency in Verilog

Pipelining places registers between combinational operations to divide work across cycles. It can improve attainable clock frequency at the cost of additional latency and state. Keep control signals aligned with their data, and distinguish latency from throughput: a pipeline may accept new work every cycle while each result takes multiple cycles to emerge.

Worked example

The first register captures a sum and the second captures a doubled previous sum. Valid information is shifted through two stages alongside the data. A transaction sampled at one edge becomes a valid output after traversing both register stages.

module pipeline(input clk,reset,valid_in,input [3:0] a,b,
                output reg [5:0] y,output reg valid_out);
  reg [4:0] sum;reg valid_sum;
  always @(posedge clk) begin
    if(reset) begin sum<=0;y<=0;valid_sum<=0;valid_out<=0;end
    else begin
      sum<={1'b0,a}+{1'b0,b};
      y<={sum,1'b0};
      valid_sum<=valid_in;valid_out<=valid_sum;
    end
  end
endmodule

What to watch for

Adding data registers without matching valid or control delays can produce numerically plausible results associated with the wrong transaction.

Try it yourself

Can a two-stage pipeline produce one result per clock?

Answer: Yes, once filled, if every stage accepts work each cycle. Its per-transaction latency is still separate from its sustained throughput.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.