Mealy and Moore RTL in Verilog

Moore-style outputs depend on the current state, while Mealy-style outputs depend on state and current inputs. This distinction affects when outputs may change and whether combinational input glitches can propagate. Registering an output changes its timing contract, so define latency and pulse behavior before choosing a coding style.

Worked example

busy is a state-only output. accept also depends on request and can change between clock edges while the machine is idle. The example isolates the output-decoding distinction without implementing the transition process.

module output_decode(input state_busy,request,output busy,accept);
  assign busy=state_busy;
  assign accept=!state_busy & request;
endmodule

What to watch for

A combinational accept signal is not automatically a full-cycle registered pulse. Consumers must sample it according to an explicit interface contract.

Try it yourself

Can a Mealy output change when no clock edge occurs?

Answer: Yes, if a relevant input changes while the current state remains fixed. Register the signal if the interface requires registered timing.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.