Directed stimulus in Verilog

Directed stimulus is a planned sequence chosen to exercise specific requirements. Start with reset and normal cases, then target boundaries and conflicting controls. A list of changing inputs is not sufficient unless you know what result should follow each step and when that result should be observed.

Worked example

Four input combinations exercise a complete two-input XOR truth table. The delay allows the continuous assignment to settle before each result is displayed. This tiny exhaustive test is directed; a larger design needs a structured test plan.

module example;
reg a,b;wire y;
integer k;
assign y=a ^ b;
initial begin
  for(k=0;k<4;k=k+1) begin
    {a,b}=k[1:0];#1;
    $display("a=%b b=%b y=%b",a,b,y);
  end
  $finish;
end
endmodule

What to watch for

A waveform that looks busy can still miss the full, empty, reset-overlap or last-item behavior that contains the bug. Tie stimulus to explicit requirements.

Try it yourself

How many binary input combinations exist for a two-input gate?

Answer: Four. Testing 00, 01, 10 and 11 is exhaustive for its binary truth table, though separate unknown-state checks may also be useful.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.