Sensitivity lists and event controls in Verilog

An event control suspends a process until a selected change occurs. A combinational sensitivity list must include every signal the process reads, or simulation may miss a required reevaluation. Verilog-2001's @* reduces manual list errors. A clock-edge event control instead describes when state is sampled.

Worked example

Changing either a or b causes the combinational expression to be evaluated. An explicit always @(a) block would omit changes to b and could simulate differently from the intended combinational circuit.

module sensitive(input a,b,output reg y);
  always @* begin
    y=a | b;
  end
endmodule

What to watch for

@* is not a reset or initialization guarantee. Functions with hidden external reads and unusual constructs deserve careful tool-specific review; pass dependencies as explicit function arguments.

Try it yourself

Why can always @(a) y=a & b be a simulation bug?

Answer: If only b changes, the process does not wake up. The modeled output can remain stale even though the intended gate output should change.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.