If, case, casez and casex in Verilog

if describes a conditional choice. case compares alternatives; casez allows z and question-mark positions to act as wildcards, while casex also treats x as a wildcard. Wildcards can hide unknown control inputs, so use them sparingly and make intended priority and default behavior explicit.

Worked example

A normal case statement makes a four-way selector. The default branch provides a value when select contains an unlisted simulation state, avoiding a retained previous y in this combinational process.

module choose(input [1:0] select, input a,b,c,d,output reg y);
  always @* begin
    case(select)
      2'd0:y=a; 2'd1:y=b; 2'd2:y=c; 2'd3:y=d;
      default:y=1'b0;
    endcase
  end
endmodule

What to watch for

casex can make an uninitialized selector match an apparently valid branch. It is not a general-purpose cure for simulation x values.

Try it yourself

Does the order of overlapping wildcard case items matter?

Answer: Yes. The first matching item is selected. Overlapping patterns can therefore encode priority, which must be intentional and tested.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.