Reduction, shifts and concatenation in Verilog

Reduction operators combine every bit of a vector into one result. Concatenation joins bit fields without arithmetic, while replication repeats a field a constant number of times. Shifts move bit positions; arithmetic right shift sign-fills only when the left operand has the intended signed type.

Worked example

Reduction XOR computes odd parity of the input bits. The concatenation creates a four-bit value by joining a two-bit prefix and suffix. The replicated zero field shows explicit construction of a wider bit pattern.

module example;
reg [3:0] data;
initial begin
  data=4'b1011;
  $display("parity=%b joined=%b",^data,{2'b10,2'b01}); // 1, 1001
  $display("extended=%b",{{4{1'b0}},data}); // 00001011
  $finish;
end
endmodule

What to watch for

A shift's result width is tied to expression sizing; shifting left does not automatically allocate extra bits to hold overflow.

Try it yourself

What is &4'b1110?

Answer: Zero. Reduction AND is one only when every input bit is one; the low bit in this vector is zero.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.