Gate primitives in Verilog

Gate primitives provide a structural description at the Boolean gate level. Built-in gates such as and, or and not connect nets using positional terminals. Primitive outputs come first, followed by their inputs. This is useful for learning connectivity and small gate models, although larger RTL is usually clearer at a higher abstraction level.

Worked example

The first primitive forms a product term. The second inverts it, so the complete network is a NAND function. Draw the two gates and compare the structural expression with assign y = ~(a & b).

module gates(input a,b, output y);
  wire product;
  and u_and(product,a,b);
  not u_not(y,product);
endmodule

What to watch for

Primitive terminal ordering differs from an arbitrary user module interface. Check the language-defined order instead of guessing from signal names.

Try it yourself

What is the output of this network when a and b are both one?

Answer: The AND output is one and the inverter output is zero. For any other binary input combination, the network output is one.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.