RAM and ROM modeling in Verilog

A Verilog memory declaration describes an array, but its access processes determine read and write behavior. Combinational ROM lookup, asynchronous RAM reads and registered reads imply different interfaces. A synthesis tool may infer dedicated memory resources only when the description matches the target's supported templates.

Worked example

This ROM uses a complete combinational case statement. Every address has a value, including a default for unknown address states in simulation. It illustrates lookup behavior without depending on a memory initialization file.

module small_rom(input [1:0] address,output reg [7:0] data);
  always @* begin
    case(address)
      2'd0:data=8'h12;2'd1:data=8'h34;
      2'd2:data=8'h56;2'd3:data=8'h78;
      default:data=8'h00;
    endcase
  end
endmodule

What to watch for

A legal array declaration does not guarantee block RAM inference. Compare your process structure with the synthesis tool's memory templates and review the resulting resource report.

Try it yourself

Is a combinational ROM output necessarily registered?

Answer: No. This example has no clock or output register. A registered ROM would need a clocked read process and a different latency contract.

How to study this topic

Save the example in a .v file and identify its top module before compiling. Separate stimulus and observation from synthesizable RTL. Change one input, width or boundary condition at a time, predict the result, and compare that prediction with simulation. A syntax check does not establish synthesis support or timing closure.