Shift-register names describe their input and output arrangement: serial-in serial-out, serial-in parallel-out, parallel-in serial-out, and parallel-in parallel-out. A serial transfer moves one bit per clock event. A parallel interface presents or captures several bits together.
Worked example
In a four-bit SIPO register using new Q = {old Q[2:0], serial input}, begin at 0000 and enter bits 1, 0, 1, 1. The successive words are 0001, 0010, 0101 and 1011. After four edges, all entered bits are available in parallel.
What to watch for
Bit order depends on the selected shift direction and indexing. Write the update rule before predicting a waveform or connecting a serial protocol.
Try it yourself
Using that update rule, what follows Q = 0101 when the next serial bit is zero?
Answer: Q becomes 1010: retain the old low three bits 101, move them left and insert zero at the right.
How to study this topic
Define the reset state and update rule before tracing a sequence. List several successive states by hand and check the wraparound. Bit direction, enable behavior and illegal-state handling are part of the specification.
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Digital Electronics