A register stores several bits together. A parallel load captures the entire input word on one clock event. A load enable decides whether to accept new data or keep the stored word. The enable belongs to the data-update rule and need not gate the clock itself.
Worked example
A four-bit register starts at 0010. At an active edge, input D = 1011 and enable = 1, so Q becomes 1011. On the next edge, D = 0000 but enable = 0, so Q remains 1011. Each bit follows the same capture-or-hold choice.
What to watch for
Do not casually form a clock by ANDing it with enable. A changing enable can create unwanted clock pulses; use a data enable or an approved clock-gating structure.
Try it yourself
What next-state equation describes one enabled register bit?
Answer: Qnext = enable ? D : Q. In words, load D when enabled and otherwise hold the old value.
How to study this topic
Define the reset state and update rule before tracing a sequence. List several successive states by hand and check the wraparound. Bit direction, enable behavior and illegal-state handling are part of the specification.
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Digital Electronics