Race-around describes repeated toggling in a level-sensitive JK arrangement when J = K = 1 and the active clock interval permits feedback to act several times. Master-slave storage uses two stages controlled in opposite phases so the externally visible state update is isolated from repeated same-phase feedback.
Worked example
If a level-sensitive JK stage toggles after a small feedback delay while its clock stays active much longer, its output may toggle again before the clock closes. The final state depends on timing. A suitable master-slave or edge-triggered arrangement prevents that repeated update during one intended clock event.
What to watch for
Race-around is not the general name for every race condition. Modern device behavior and clock requirements must be read from the particular implementation's specification.
Try it yourself
Why does shortening an active clock pulse not provide a universal design solution?
Answer: Its width would have to satisfy all device timing limits and variations. Choosing an appropriate storage architecture is more reliable than relying on an accidental delay.
How to study this topic
Write the old state, input values and next state in separate columns. Mark the active clock edge or enable interval. This prevents a stored value from being confused with an input that is merely waiting to be captured.
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Digital Electronics