A synchronous reset or set changes state at an active clock edge. An asynchronous control can change the stored state without waiting for a clock edge. The choice affects both system behavior and timing. Reset polarity and simultaneous-control priority must be defined explicitly.
Worked example
For a synchronous active-high reset, a D flip-flop with reset = 1 becomes zero on the next active edge. If the clock stops, it may keep its old state. An asynchronous reset can clear it immediately even when the clock is stopped.
What to watch for
Asynchronous reset release must satisfy recovery and removal requirements. Systems often assert reset asynchronously and synchronize its release separately in each clock domain.
Try it yourself
Which reset type can clear a register while its clock is stopped?
Answer: An asynchronous reset, provided the device supports it and its electrical and pulse-width requirements are satisfied.
How to study this topic
Write the old state, input values and next state in separate columns. Mark the active clock edge or enable interval. This prevents a stored value from being confused with an input that is merely waiting to be captured.
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Digital Electronics