In a ripple counter, one stage's output clocks the next stage. This can build a simple divider, but the state bits do not all change at the same time. A transition may ripple through several stages before the final binary count settles.
Worked example
During the intended transition from 0111 to 1000, a possible delay sequence is 0111 → 0110 → 0100 → 0000 → 1000 for a suitable ripple arrangement. An asynchronous decoder observing those intermediate values can briefly report counts that were not intended as stable states.
What to watch for
The exact transient sequence depends on edge polarity and wiring. Avoid treating a ripple counter's output as an instantly coherent synchronous word.
Try it yourself
Why can a decoder connected to a ripple counter glitch?
Answer: Several counter bits change at different times. Intermediate combinations can briefly satisfy the decoder's logic before the final count settles.
How to study this topic
Define the reset state and update rule before tracing a sequence. List several successive states by hand and check the wraparound. Bit direction, enable behavior and illegal-state handling are part of the specification.
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Digital Electronics