A synchronous counter clocks all its storage elements from the same clock. Combinational next-state logic decides which bits change. For a binary up-counter built with T flip-flops, each bit toggles when all lower bits are one; the lowest bit toggles every enabled count.
Worked example
For a three-bit counter, T0 = 1, T1 = Q0, and T2 = Q1 AND Q0. At Q = 011, all three T inputs are one, so the next active edge produces 100. The clock does not propagate through Q0 and Q1 to reach the upper stage.
What to watch for
Outputs still have finite clock-to-Q delays. Synchronous does not mean that every physical output changes at the exact same instant; it means their state updates share a clock event.
Try it yourself
What follows state 101 in a three-bit binary up-counter?
Answer: 110. The low bit toggles, the next bit toggles because old Q0 was one, and the high bit holds.
How to study this topic
Define the reset state and update rule before tracing a sequence. List several successive states by hand and check the wraparound. Bit direction, enable behavior and illegal-state handling are part of the specification.
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Digital Electronics