The critical setup path is the path that requires the longest interval between launch and capture events. In a simple same-clock model, the period must cover launch clock-to-Q, maximum combinational delay and capture setup time. Additional clock uncertainty and skew must be included in a real timing analysis.
Worked example
With clock-to-Q = 1 ns, logic delay = 6 ns and setup = 1 ns, the basic minimum period is 8 ns. Its reciprocal is 125 MHz. If the design additionally reserves 1 ns of uncertainty, the required period becomes 9 ns and the corresponding bound is about 111 MHz.
What to watch for
Hold uses minimum path delays, not this maximum-delay sum. A design can pass setup but still need fixes for a very fast path.
Try it yourself
What basic period is needed for 2 ns clock-to-Q, 5 ns logic and 1 ns setup?
Answer: 8 ns before adding clock skew, uncertainty and other required margins.
How to study this topic
Draw the launch edge, capture edge and data transition on one timeline. Use guaranteed limits for real timing checks. Identify the clock domain and signal type before choosing a synchronizer or crossing protocol.
Explore related programmes
These recorded programmes are upcoming. This article is general educational content, not a syllabus or course sample.
Digital Electronics