Setup time is the required stable-data interval before a sampling edge. Hold time is the required stable-data interval after it. Clock-to-Q is the delay from the active clock edge to the registered output response. These three values describe different portions of a register-to-register timing path.
Worked example
If a flip-flop requires 2 ns setup and 1 ns hold around an edge at 10 ns, its input must be stable from 8 ns through 11 ns. If clock-to-Q is 3 ns, a corresponding output response occurs around 13 ns under the stated timing model.
What to watch for
Violating setup or hold does not produce a useful guaranteed output value. Use the specified worst-case limits and operating conditions rather than a convenient typical number.
Try it yourself
For an edge at 20 ns and setup time 3 ns, when must the new data already be stable?
Answer: By 17 ns, and it must remain stable through the required hold interval after the edge.
How to study this topic
Draw the launch edge, capture edge and data transition on one timeline. Use guaranteed limits for real timing checks. Identify the clock domain and signal type before choosing a synchronizer or crossing protocol.
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Digital Electronics