Counters can measure events, generate periodic enables or divide clock frequency. A continuously toggling flip-flop divides the input frequency by two. A binary counter's successive bits divide by larger powers of two, while a modulo counter can generate a pulse every chosen number of cycles.
Worked example
With a 16 MHz clock, the lowest bit of a continuously running binary counter toggles each edge and has an 8 MHz full-cycle frequency. The next bit is 4 MHz. A modulo-1000 terminal-count enable occurs once per 1000 input cycles, giving 16,000 pulses per second.
What to watch for
A terminal-count pulse is not automatically a 50% duty-cycle clock. In synchronous systems, prefer a clock enable when a slower update rate is sufficient.
Try it yourself
At 1 MHz, how often does a pulse occur for a modulo-100 counter?
Answer: 10,000 times per second, because 1,000,000 / 100 = 10,000. Each pulse can enable a slower operation.
How to study this topic
Define the reset state and update rule before tracing a sequence. List several successive states by hand and check the wraparound. Bit direction, enable behavior and illegal-state handling are part of the specification.
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Digital Electronics