Clock skew is a difference in clock arrival time between registers. Jitter is variation in the timing of clock edges. They change the time available for a path. Define the sign of skew explicitly before deciding whether it helps or hurts setup or hold.
Worked example
Let skew mean capture-clock arrival minus launch-clock arrival. If the capture edge arrives 0.5 ns later, a same-cycle hold check becomes harder by that amount, while the next-cycle setup path gains time in the simple model. An early capture edge has the opposite effect.
What to watch for
Helpful skew for one check may hurt another. Jitter and uncertainty consume timing margin and must not be counted as reliably favorable changes.
Try it yourself
If the next capture edge arrives earlier than expected, what happens to setup time available to the data path?
Answer: It decreases. The data must settle sooner, so the setup check becomes harder.
How to study this topic
Draw the launch edge, capture edge and data transition on one timeline. Use guaranteed limits for real timing checks. Identify the clock domain and signal type before choosing a synchronizer or crossing protocol.
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