Metastability can occur when a storage element samples a signal near a setup or hold violation. Its output may take unusually long to settle to a valid level. A synchronizer gives that output additional settling time before the receiving logic uses it.
Worked example
For a slowly changing asynchronous single-bit level, use two receiving-clock flip-flops in series. The first samples the incoming level; the second samples the first on the next edge. The intervening cycle reduces the probability that unresolved behavior reaches downstream logic.
What to watch for
A synchronizer reduces risk rather than eliminating it. A two-stage level synchronizer is not enough to preserve an arbitrarily short pulse or an independently sampled multi-bit word.
Try it yourself
Why should ordinary logic avoid using the first synchronizer stage's output?
Answer: That stage is the one most exposed to metastability. Downstream logic should use the settled later-stage signal according to the CDC design.
How to study this topic
Draw the launch edge, capture edge and data transition on one timeline. Use guaranteed limits for real timing checks. Identify the clock domain and signal type before choosing a synchronizer or crossing protocol.
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