SystemVerilog Projects

About this course

Apply SystemVerilog Advanced through three progressively richer verification exercises: a synchronous FIFO, a round-robin arbiter, and a small ready/valid register peripheral. Begin each exercise by defining its interface, reset contract, legal traffic, and observable results, then derive a verification plan before constructing stimulus and checkers. Reuse transaction classes, drivers, monitors, reference models, assertions, and coverage collectors while adapting them to each DUT's timing and ordering rules. Progress from directed boundary tests to constrained random scenarios, seed regressions, and evidence-based gap analysis. Debug both DUT and testbench mistakes and document remaining limitations instead of equating a passing run with complete verification. These are proposed learning exercises with explicit scope, not claims of delivered commercial IP. The work uses plain SystemVerilog; UVM remains a separate follow-on methodology course.

Learning objectives

• Convert a bounded DUT specification into traceable test, assertion, and coverage goals.
• Construct a self-checking synchronous FIFO environment with a queue-based reference model.
• Verify round-robin arbitration with an independently maintained priority model and bounded-service assumptions.
• Verify a ready/valid register peripheral against a defined memory-map and handshake contract.
• Adapt reusable transaction, driver, monitor, scoreboard, and configuration classes across exercises.
• Exercise reset, boundary conditions, concurrent traffic, and backpressure through reproducible tests.
• Diagnose injected defects and distinguish DUT failures from testbench mistakes.
• Produce a regression and coverage review that records evidence, exclusions, and unresolved gaps.

Curriculum

Prerequisites

• SystemVerilog classes, object ownership, constraints, and reproducible randomization.
• Mailboxes, concurrent-process control, clocking blocks, and reset-aware synchronization.
• Functional coverage, temporal assertion sampling, and scoreboard construction.
• Ability to diagnose simulation mismatches using logs and waveforms.

Course requirements

• A SystemVerilog simulator with checked support for classes, constraints, interfaces, clocking blocks, SVA, and functional covergroups used by these exercises.
• Appropriately licensed local access or an authorized browser-based simulator account with suitable execution and coverage-report capabilities.
• A text editor, waveform viewer, and writable storage for source, logs, seeds, and coverage artifacts.
• A shell or basic scripting setup to run repeatable test-and-seed matrices and collect failures.
• Access to small editable RTL DUTs or the ability to implement the specified exercise DUTs; Icarus Verilog or Verilator alone should not be assumed sufficient for the complete environment.

Who this course is for

• Learners who have completed advanced SystemVerilog verification concepts.
• Students seeking structured practice connecting specifications to self-checking environments.
• Engineers preparing to study UVM after constructing language-level verification components.

Practice projects

Planned exercises for applying the syllabus.

1. Synchronous FIFO verification

   Proposed exercise: verify a single-clock parameterized FIFO with synchronous reset, specified read latency, and explicit simultaneous push/pop behavior. Build transactions, drivers, monitors, an independent queue model, boundary assertions, occupancy coverage, and seed regressions; asynchronous FIFO CDC is outside scope.

2. Round-robin arbiter verification

   Proposed exercise: verify a parameterized arbiter with grants accepted on a documented clocked handshake and priority advancing only on acceptance. Check grant legality and rotation using a reference priority model, then cover contention, idle cycles, reset, and bounded-service cases under stated assumptions.

3. Ready/valid register peripheral verification

   Proposed exercise: verify a small single-clock register block with one in-order outstanding request, stable request fields while stalled, defined response backpressure, reset values, byte enables, and invalid-address responses. Create a register reference model, protocol assertions, scenario coverage, and a reproducible review package; no APB or UART compliance is claimed.

Curriculum references

• Accellera: Available IEC/IEEE Standards

  Language and methodology scope reference; the DUT specifications and exercises are original pedagogical proposals.

• Siemens Verification Academy: Introduction to Functional Coverage

  Supports using distinct coverage metrics to assess verification progress; no universal coverage percentage or sign-off guarantee is claimed.

• Siemens Verification Horizons: DAC 2020 newsletter

  Official source identifying deeper SVA execution semantics relevant to validating project properties.

• Verilator: Input Languages

  Supports version-specific tool capability checks for advanced verification exercises.

• Icarus Verilog: Official README

  Supports the limitation that selecting SystemVerilog mode does not establish complete advanced verification support.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions