SystemVerilog Advanced

About this course

Develop a reusable verification environment using SystemVerilog language features after completing the class, interface, and simulation foundations. Start by strengthening object ownership and polymorphism, then construct legal randomized transactions with checked constraint solving and reproducible seeds. Coordinate concurrent components through mailboxes, events, and semaphores while handling reset, timeouts, and orderly shutdown. Turn a written verification plan into functional covergroups and temporal assertions, paying particular attention to sampling, vacuity, and what each metric can actually demonstrate. Integrate a driver, monitor, reference model, and scoreboard, then investigate failures through focused regressions and documented coverage gaps. The environment remains plain SystemVerilog so that language concepts are visible before a later UVM course introduces a standardized framework. A compatible simulator is required for the advanced exercises; feature availability and licensing must be checked in advance.

Learning objectives

• Design class hierarchies with explicit object ownership, copying, and virtual dispatch.
• Write legal constrained randomized stimulus and diagnose failed randomization calls.
• Coordinate concurrent components with bounded waiting and deterministic reset handling.
• Create requirement-linked covergroups with deliberate sampling and meaningful crosses.
• Write and validate temporal assertions with correct sampling and reset semantics.
• Connect a monitor, reference model, and scoreboard with explicit ordering rules.
• Run reproducible seed regressions and explain uncovered or waived verification goals.
• Explain which plain SystemVerilog patterns prepare for a separate UVM methodology course.

Curriculum

Prerequisites

• SystemVerilog types, arrays, packages, tasks, functions, and automatic lifetimes.
• Classes, constructors, inheritance basics, handles, and virtual interfaces.
• Interface and clocking-block connections, reset sequencing, and self-checking directed tests.
• Verilog RTL simulation and waveform-based debugging.

Course requirements

• A compatible SystemVerilog simulator supporting the required class features, constraint solver, covergroups, concurrent assertions, and clocking blocks; run feature checks for the installed version.
• Appropriately licensed local simulator access or an authorized browser-based service with the required capabilities and run limits.
• Waveform and log inspection tools, plus access to the simulator's coverage reports or database utilities.
• A shell and basic scripting environment for passing seeds, collecting exit status, and organizing regression artifacts.
• Icarus Verilog and Verilator alone must not be assumed sufficient for every exercise; their SystemVerilog support is partial and changes across versions.

Who this course is for

• Learners comfortable with basic SystemVerilog classes, interfaces, and clocking blocks.
• Verification learners preparing to build reusable environments before learning UVM.
• RTL engineers adding constrained stimulus, functional coverage, and assertions to simulation.

Practice projects

Planned exercises for applying the syllabus.

1. Constrained transaction generator

   Proposed exercise: generate bounded packet fields and legal operation sequences, detect conflicting constraints, preserve failing seeds, and compare intended versus observed distributions.

2. Coverage-guided register-slice environment

   Proposed exercise: extend a specified ready/valid register-slice testbench with concurrent stimulus and checking, randomized stalls, reset recovery, transfer properties, functional coverage, and a reproducible regression report.

Curriculum references

• Accellera: Available IEC/IEEE Standards

  Separates SystemVerilog language standardization from UVM methodology standardization.

• Siemens Verification Academy: SystemVerilog OOP course announcement

  Official academy explanation of classes, inheritance, and polymorphism as foundations usable before UVM.

• Siemens Verification Academy: Introduction to Functional Coverage

  Supports coverage classifications and verification-metric planning; complete training content may require access.

• Siemens Verification Horizons: DAC 2020 newsletter

  Points to technical treatment of the SVA engine and independent assertion attempts.

• Verilator: Input Languages

  Explicitly documents limited classes and partial assertion and functional-coverage support.

• Icarus Verilog: Official README

  Warns that SystemVerilog support is incomplete; language mode is not a guarantee that every verification construct works.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions