SystemVerilog Basics

About this course

Build on your Verilog knowledge to write clear SystemVerilog models and small, self-checking testbenches. Begin with data types, signed expressions, arrays, strings, and structured data before moving into procedures, packages, interfaces, and clocking blocks. Explore how simulation scheduling affects driving and sampling, then introduce classes through transactions, constructors, methods, and object ownership. Each stage connects a language feature to a practical verification task, including organizing stimulus, observing a handshake, and comparing expected results. The final exercise assembles a compact transaction-based environment without UVM. This course establishes the language and object-oriented foundations needed for SystemVerilog Advanced; comprehensive constrained random verification, functional coverage, and temporal assertions are developed in that next course. Exercises require a simulator whose supported features match the selected lessons.

Learning objectives

• Select two-state and four-state types and explain width, signedness, and unknown-value behavior.
• Model transaction fields using packed structures, enumerations, arrays, queues, and strings.
• Write tasks and functions with deliberate argument directions and variable lifetimes.
• Organize shared declarations with packages and connect a testbench through an interface.
• Use a clocking block to make signal driving and sampling intent explicit.
• Create classes, construct objects, and distinguish a handle assignment from an object copy.
• Build and debug a small self-checking transaction-based environment without UVM.

Curriculum

Prerequisites

• Verilog modules, ports, parameters, and basic testbench construction.
• Combinational and sequential RTL, clocks, reset, and blocking versus nonblocking assignments.
• Ability to compile a design, read a waveform, and locate a simple simulation failure.

Course requirements

• Access to a SystemVerilog simulator with support for the course's interfaces, clocking blocks, packages, and basic classes; check the installed version before starting.
• A local installation with appropriate licensing, or an authorized browser-based simulator account where access permits the required features.
• A text editor, writable project directory, and a way to inspect simulation logs and waveforms.
• Icarus Verilog or Verilator may support selected introductory exercises, but neither should be assumed sufficient for the full sequence; check four-state behavior and class support explicitly.

Who this course is for

• Learners who can already write and simulate Verilog RTL.
• Students moving from module-based testbenches toward verification programming.
• RTL engineers seeking a structured introduction to SystemVerilog language features.

Practice projects

Planned exercises for applying the syllabus.

1. Typed packet collection exercise

   Proposed exercise: represent small packets using enumerations, packed headers, queues, and helper functions; check field conversions and queue ordering with explicit expected results.

2. Handshake transaction mini-environment

   Proposed exercise: drive a specified single-clock ready/valid register slice through an interface, observe accepted transfers, and compare their order and payloads using small classes and a queue model.

Curriculum references

• Accellera: Available IEC/IEEE Standards

  Identifies IEEE 1800-2023 as the SystemVerilog standard and distinguishes it from the separate UVM standard.

• Siemens Verification Academy: Verilog Basics for SystemVerilog Constrained Random Verification

  Supports establishing Verilog and simulation foundations before advanced verification programming.

• Accellera: SystemVerilog Design Tutorial

  Official technical reference for design-oriented language choices; an older tutorial rather than the current language standard.

• Verilator: Input Languages

  Documents current feature limitations, including limited class support and predominantly two-state simulation.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions