Chiprion.
Back
Courses SystemVerilog

SystemVerilog Basics

Build on your Verilog knowledge to write clear SystemVerilog models and small, self-checking testbenches.

10 sectionsSelf-paced learning

About this course

Build on your Verilog knowledge to write clear SystemVerilog models and small, self-checking testbenches. Begin with data types, signed expressions, arrays, strings, and structured data before moving into procedures, packages, interfaces, and clocking blocks. Explore how simulation scheduling affects driving and sampling, then introduce classes through transactions, constructors, methods, and object ownership. Each stage connects a language feature to a practical verification task, including organizing stimulus, observing a handshake, and comparing expected results. The final exercise assembles a compact transaction-based environment without UVM. This course establishes the language and object-oriented foundations needed for SystemVerilog Advanced; comprehensive constrained random verification, functional coverage, and temporal assertions are developed in that next course. Exercises require a simulator whose supported features match the selected lessons.

Where to start

Build the knowledge in these courses first, or bring equivalent practical experience:

What you’ll learn

  • Select two-state and four-state types and explain width, signedness, and unknown-value behavior.
  • Model transaction fields using packed structures, enumerations, arrays, queues, and strings.
  • Write tasks and functions with deliberate argument directions and variable lifetimes.
  • Organize shared declarations with packages and connect a testbench through an interface.
  • Use a clocking block to make signal driving and sampling intent explicit.
  • Create classes, construct objects, and distinguish a handle assignment from an object copy.
  • Build and debug a small self-checking transaction-based environment without UVM.

Course syllabus

10 sections · 50 topics

01. From Verilog to SystemVerilog5 topics
  1. Review module-based RTL and testbench responsibilities using an existing Verilog example.
  2. Separate synthesizable modeling constructs from simulation-only verification code.
  3. Configure SystemVerilog compilation mode, file order, time units, and time precision.
  4. Read compile diagnostics and establish a repeatable compile-run-waveform workflow.
  5. Identify the language foundations covered here and the advanced verification topics that follow.
02. Types, values, and expressions5 topics
  1. Compare logic and bit with integer types, nets, variables, and default initialization.
  2. Track X and Z values using four-state comparisons and appropriate unknown checks.
  3. Trace signedness, sizing, extension, truncation, and mixed-type expressions.
  4. Use explicit casts, typedef declarations, and local parameters to communicate intent.
  5. Apply enumerations to states and operation codes with deliberate conversion checks.
03. Packed data and structured fields5 topics
  1. Distinguish packed vectors from unpacked storage and interpret dimension ordering.
  2. Build packed and unpacked structures for related transaction fields.
  3. Compare ordinary unions with packed unions and identify representation assumptions.
  4. Use slicing, indexed part selects, concatenation, and streaming on small examples.
  5. Inspect field widths and layouts with query functions and readable diagnostic output.
04. Arrays, queues, and strings5 topics
  1. Declare and traverse fixed-size and multidimensional unpacked arrays.
  2. Allocate, resize, and copy dynamic arrays while checking retained data.
  3. Use associative arrays for sparse lookup and handle missing keys explicitly.
  4. Apply queues, foreach loops, and array methods to ordered expected results.
  5. Format messages and parse simple text using string operations and conversion functions.
05. Procedures and variable lifetimes5 topics
  1. Choose always_comb, always_ff, and always_latch for their intended modeling roles.
  2. Write functions for value computation and tasks for operations that consume simulation time.
  3. Compare input, output, inout, ref, and const ref argument behavior.
  4. Distinguish static and automatic lifetimes, including reentrant helper procedures.
  5. Use loops, break, continue, and return without creating nonterminating testbench activity.
06. Packages and simulation organization5 topics
  1. Place reusable types and helper procedures in packages with explicit imports.
  2. Distinguish package scope, module scope, class scope, and compilation-unit visibility.
  3. Separate source inclusion from package import and document compilation dependencies.
  4. Review active and nonblocking update behavior through a small race example.
  5. Generate clocks, apply reset, and terminate a test with clear pass and failure conditions.
07. Interfaces and clocking blocks5 topics
  1. Bundle related signals in a parameterized interface with a documented handshake.
  2. Use modports to state the intended direction and role of an interface connection.
  3. Introduce clocking events, input sampling, output driving, and skew choices.
  4. Connect module-based drivers and monitors without relying on arbitrary delay fixes.
  5. Observe accepted transfers and reset behavior in a ready/valid waveform.
08. Classes and transaction objects5 topics
  1. Declare class properties, methods, and constructors for a small transaction.
  2. Allocate an object with new and identify null-handle access failures.
  3. Distinguish object identity, handle assignment, shallow copying, and explicit field copying.
  4. Use local and protected visibility where it clarifies ownership and access.
  5. Introduce inheritance, super, and virtual methods through one small specialization.
09. Connecting objects to signals5 topics
  1. Pass a virtual interface into a class-based driver or monitor.
  2. Translate a directed transaction into clocked pin activity through the interface.
  3. Capture a fresh observed transaction for each completed handshake.
  4. Compare observed payloads against a queue-based expected sequence.
  5. Add readable transaction formatting, mismatch reports, and a bounded test timeout.
10. Assembling and reviewing a mini-environment5 topics
  1. Separate test setup, directed stimulus, driving, monitoring, and checking responsibilities.
  2. Exercise empty traffic, back-to-back transfers, backpressure, and reset cases from a written checklist.
  3. Debug injected field, ordering, and reset mistakes using logs and waveforms.
  4. Record a reproducible command, simulator version, and pass/fail summary.
  5. Review object ownership and sampling choices before progressing to constrained randomness, coverage, and temporal assertions in Advanced.

Course requirements

  • Access to a SystemVerilog simulator with support for the course's interfaces, clocking blocks, packages, and basic classes; check the installed version before starting.
  • A local installation with appropriate licensing, or an authorized browser-based simulator account where access permits the required features.
  • A text editor, writable project directory, and a way to inspect simulation logs and waveforms.
  • Icarus Verilog or Verilator may support selected introductory exercises, but neither should be assumed sufficient for the full sequence; check four-state behavior and class support explicitly.

Prerequisites

  • Verilog modules, ports, parameters, and basic testbench construction.
  • Combinational and sequential RTL, clocks, reset, and blocking versus nonblocking assignments.
  • Ability to compile a design, read a waveform, and locate a simple simulation failure.

Who this course is for

  • Learners who can already write and simulate Verilog RTL.
  • Students moving from module-based testbenches toward verification programming.
  • RTL engineers seeking a structured introduction to SystemVerilog language features.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Typed packet collection exercise

    Proposed exercise: represent small packets using enumerations, packed headers, queues, and helper functions; check field conversions and queue ordering with explicit expected results.

  2. Handshake transaction mini-environment

    Proposed exercise: drive a specified single-clock ready/valid register slice through an interface, observe accepted transfers, and compare their order and payloads using small classes and a queue model.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

Course outline and pricing are subject to confirmation before enrolment opens.