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SystemVerilog Projects

Apply SystemVerilog Advanced through three progressively richer verification exercises: a synchronous FIFO, a round-robin arbiter, and a small ready/valid register peripheral.

10 sectionsSelf-paced learning

About this course

Apply SystemVerilog Advanced through three progressively richer verification exercises: a synchronous FIFO, a round-robin arbiter, and a small ready/valid register peripheral. Begin each exercise by defining its interface, reset contract, legal traffic, and observable results, then derive a verification plan before constructing stimulus and checkers. Reuse transaction classes, drivers, monitors, reference models, assertions, and coverage collectors while adapting them to each DUT's timing and ordering rules. Progress from directed boundary tests to constrained random scenarios, seed regressions, and evidence-based gap analysis. Debug both DUT and testbench mistakes and document remaining limitations instead of equating a passing run with complete verification. These are proposed learning exercises with explicit scope, not claims of delivered commercial IP. The work uses plain SystemVerilog; UVM remains a separate follow-on methodology course.

Where to start

Build the knowledge in these courses first, or bring equivalent practical experience:

What you’ll learn

  • Convert a bounded DUT specification into traceable test, assertion, and coverage goals.
  • Construct a self-checking synchronous FIFO environment with a queue-based reference model.
  • Verify round-robin arbitration with an independently maintained priority model and bounded-service assumptions.
  • Verify a ready/valid register peripheral against a defined memory-map and handshake contract.
  • Adapt reusable transaction, driver, monitor, scoreboard, and configuration classes across exercises.
  • Exercise reset, boundary conditions, concurrent traffic, and backpressure through reproducible tests.
  • Diagnose injected defects and distinguish DUT failures from testbench mistakes.
  • Produce a regression and coverage review that records evidence, exclusions, and unresolved gaps.

Course syllabus

10 sections · 54 topics

01. Project contracts and reusable verification structure5 topics
  1. Define the three DUT interfaces, parameter limits, clock/reset assumptions, and observable pass criteria.
  2. Create a requirement matrix linking each behavior to directed tests, assertions, and coverage.
  3. Establish shared transaction formatting, configuration, object ownership, and reporting conventions.
  4. Separate generator, driver, monitor, reference model, scoreboard, and coverage responsibilities.
  5. Prepare a simulator capability smoke check and a reproducible repository and command layout.
02. FIFO specification and directed bring-up5 topics
  1. Specify FIFO depth, width, synchronous reset, read response latency, and flag timing.
  2. Define acceptance rules for full, empty, simultaneous push/pop, and rejected operations.
  3. Create FIFO transactions and clocking-block driver and monitor connections.
  4. Implement an independent queue model and compare each accepted read in order.
  5. Run reset, single transfer, fill, drain, and wraparound cases before randomized traffic.
03. FIFO assertions, coverage, and regression6 topics
  1. Add occupancy-bound, accepted-operation, flag, and reset checks consistent with the written contract.
  2. Create coverpoints for occupancy boundaries, simultaneous operations, and wraparound scenarios.
  3. Constrain bursts, idle periods, and operation mixes while checking randomization failures.
  4. Test reset with queued data and define how expected and observed state are flushed.
  5. Inject an ordering or flag defect, preserve its failing seed, and review logs and waveforms.
  6. Run a seed matrix and document covered goals, unreachable combinations, and remaining gaps.
04. Arbiter specification and reference behavior5 topics
  1. Define request width, grant representation, grant acceptance, and priority-update rules.
  2. State whether requests must remain asserted and under which conditions progress is expected.
  3. Build request-pattern transactions, a driver, and an acceptance-aware monitor.
  4. Implement an independent rotating-priority reference model with explicit reset state.
  5. Compare grants for single requesters, idle cycles, all-requester contention, and reset.
05. Arbiter properties and contention closure6 topics
  1. Assert one-hot-or-zero grants, grant-to-request consistency, and specified priority rotation.
  2. Express bounded-service checks only under documented persistent-request and acceptance assumptions.
  3. Cover requester combinations, priority positions, service sequences, and reset transitions.
  4. Generate randomized contention and delayed acceptance without violating stimulus assumptions.
  5. Inject a priority-update defect and distinguish model, assumption, and DUT failures.
  6. Run regressions and review missing contention cases and each progress property's activation.
06. Peripheral specification and verification plan5 topics
  1. Specify request and response ready/valid channels with one in-order outstanding request.
  2. Define address map, register widths, reset values, byte-enable behavior, and invalid-address responses.
  3. State field stability under stalls, write acceptance, read response timing, and reset cancellation.
  4. Create read/write transaction types and a test matrix covering legal and invalid accesses.
  5. Define reference-model update points and separate protocol checks from register-value checks.
07. Peripheral environment and self-checking traffic5 topics
  1. Build a request driver that holds fields stable until acceptance and observes response completion.
  2. Implement passive request and response monitors with explicit pairing rules.
  3. Maintain an independent register model including byte enables and reset defaults.
  4. Compare read data, response status, and ordering in the scoreboard.
  5. Bring up directed write/readback, partial writes, invalid addresses, and response stalls.
08. Peripheral assertions and scenario coverage6 topics
  1. Assert request and response stability while stalled with sampling aligned to the interface contract.
  2. Check response accounting and bounded completion only where the specification gives a bound.
  3. Cover address categories, operation types, byte-enable patterns, stalls, and error responses.
  4. Randomize legal access mixes and bounded backpressure while preserving reproducible seeds.
  5. Exercise reset during idle, a pending request, and a pending response with defined model flushing.
  6. Inject a data or response-accounting bug and demonstrate detection with a focused rerun.
09. Cross-project regression and debugging5 topics
  1. Build per-project test-and-seed matrices with timeout handling and machine-readable pass/fail status.
  2. Save simulator version, configuration, parameters, seed, and exact failing command.
  3. Reduce a randomized failure to a short sequence without losing the triggering behavior.
  4. Classify DUT, stimulus, reference-model, assertion, and infrastructure defects.
  5. Merge only compatible coverage runs and investigate uncovered requirements before changing constraints.
10. Verification evidence and design review6 topics
  1. Review requirement-to-test traceability and demonstrate that injected defects activate the intended checks.
  2. Present representative failures, repaired behavior, and regression results for all three DUTs.
  3. Explain assertion activation, vacuity checks, coverage exclusions, and untested parameter combinations.
  4. Document the assumptions behind FIFO acceptance, arbiter service bounds, and peripheral reset behavior.
  5. Package source, specifications, plans, commands, logs, and known limitations for another learner to reproduce.
  6. Identify reusable components and discuss how a later UVM course can standardize their lifecycle and connections.

Course requirements

  • A SystemVerilog simulator with checked support for classes, constraints, interfaces, clocking blocks, SVA, and functional covergroups used by these exercises.
  • Appropriately licensed local access or an authorized browser-based simulator account with suitable execution and coverage-report capabilities.
  • A text editor, waveform viewer, and writable storage for source, logs, seeds, and coverage artifacts.
  • A shell or basic scripting setup to run repeatable test-and-seed matrices and collect failures.
  • Access to small editable RTL DUTs or the ability to implement the specified exercise DUTs; Icarus Verilog or Verilator alone should not be assumed sufficient for the complete environment.

Prerequisites

  • SystemVerilog classes, object ownership, constraints, and reproducible randomization.
  • Mailboxes, concurrent-process control, clocking blocks, and reset-aware synchronization.
  • Functional coverage, temporal assertion sampling, and scoreboard construction.
  • Ability to diagnose simulation mismatches using logs and waveforms.

Who this course is for

  • Learners who have completed advanced SystemVerilog verification concepts.
  • Students seeking structured practice connecting specifications to self-checking environments.
  • Engineers preparing to study UVM after constructing language-level verification components.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Synchronous FIFO verification

    Proposed exercise: verify a single-clock parameterized FIFO with synchronous reset, specified read latency, and explicit simultaneous push/pop behavior. Build transactions, drivers, monitors, an independent queue model, boundary assertions, occupancy coverage, and seed regressions; asynchronous FIFO CDC is outside scope.

  2. Round-robin arbiter verification

    Proposed exercise: verify a parameterized arbiter with grants accepted on a documented clocked handshake and priority advancing only on acceptance. Check grant legality and rotation using a reference priority model, then cover contention, idle cycles, reset, and bounded-service cases under stated assumptions.

  3. Ready/valid register peripheral verification

    Proposed exercise: verify a small single-clock register block with one in-order outstanding request, stable request fields while stalled, defined response backpressure, reset values, byte enables, and invalid-address responses. Create a register reference model, protocol assertions, scenario coverage, and a reproducible review package; no APB or UART compliance is claimed.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

Course outline and pricing are subject to confirmation before enrolment opens.