UVM

About this course

Build a reusable SystemVerilog verification environment by understanding each UVM mechanism before combining it with the next. The course starts with objects, components, phases, and transaction models, then develops sequences, a correctly synchronized driver, passive monitoring, agents, and independent checking. Configuration and factory overrides are introduced after the basic data path is visible, making reuse decisions easier to debug. Later sections coordinate multiple interfaces, handle reset, connect a register model, and integrate assertions and functional coverage. Planned exercises culminate in a reproducible regression with failure triage and a documented coverage review. Advanced SystemVerilog knowledge is required; prior project work is useful but optional. The reference basis is IEEE 1800.2-2020 and Accellera implementation documentation, with explicit attention to simulator compatibility and differences from older UVM examples.

Learning objectives

• Construct a UVM environment with clear responsibilities for tests, environments, agents, drivers, monitors, and scoreboards.
• Model transactions and generate constrained stimulus using reusable sequences.
• Implement the sequencer-driver handshake without deadlocks or premature transaction completion.
• Connect analysis components and compare observed DUT behavior with an independent model.
• Configure virtual interfaces and agent behavior through typed configuration objects.
• Use factory overrides and coordinated sequences to vary tests without duplicating the environment.
• Integrate a register model with adapters, prediction, and register access checks.
• Use assertions, functional coverage, reproducible regressions, and debug evidence to assess verification completeness.

Curriculum

Prerequisites

• SystemVerilog classes, inheritance, polymorphism, parameterized types, and object handles.
• Constrained randomization, queues, mailboxes, events, and concurrent processes.
• Interfaces, virtual interfaces, clocking blocks, assertions, and functional coverage fundamentals.
• Self-checking RTL testbench experience; the Projects course is recommended practice rather than a required dependency.

Course requirements

• Access to a simulator with the SystemVerilog class, constrained-random, coverage, assertion, and UVM features needed by the exercises.
• A compatible UVM library and documented compile/run setup; use the simulator-supported or validated Accellera implementation.
• A code editor, terminal, waveform/log viewer, and a way to preserve test names and random seeds.
• Git and a scripting environment for launching and collecting regression results.
• Tool-specific coverage viewing or reporting access for coverage exercises; feature availability and licenses must be checked.

Who this course is for

• Learners comfortable with advanced SystemVerilog classes, interfaces, randomization, and coverage.
• Verification engineers moving from custom class-based testbenches to reusable UVM environments.
• RTL designers who want to understand block-level verification architecture and evidence.

Practice projects

Planned exercises for applying the syllabus.

1. Reusable FIFO verification agent

   Planned exercise: create transactions, sequences, a driver, and an independent monitor for a FIFO interface, then connect a reference queue and boundary-focused coverage.

2. Register-mapped peripheral environment

   Planned exercise: verify a small register-mapped peripheral using a reusable bus agent, register model, adapter, prediction, access-policy checks, and reset tests.

3. Coverage-guided verification capstone

   Planned exercise: combine coordinated traffic, reset scenarios, assertions, scoreboarding, and seeded regressions; document reproduced failures, coverage gaps, and justified exclusions.

Curriculum references

• Accellera UVM Working Group

  Identifies the IEEE 1800.2-2020 reference basis and distinguishes the API standard from its implementation.

• Accellera UVM downloads

  Official access point for reference implementations and historical UVM reference material.

• Accellera maintained uvm-core repository

  Current repository documents IEEE 1800.2-2020 alignment, kit 2020.3.1, compatibility, and deviations; record a selected release rather than assuming main is stable.

• Siemens Verification Academy UVM Cookbook

  Practical cross-check for architecture, phasing, sequence-driver connections, analysis, configuration, factory, registers, and debug; some chapters originate in older UVM versions.

• Siemens Verification Academy: UVM Sequence Items

  Supports the transaction-to-sequence-to-sequencer-to-driver stimulus relationship.

• Siemens Verification Academy: Advanced UVM

  Supports progression toward reusable environments, coordinated stimulus, and register-layer integration; used as a topic reference, not copied course content.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions