Advanced Digital IC

About this course

Move from working Verilog modules to digital blocks whose architecture, timing, interfaces, and implementation tradeoffs can be explained and measured. This course develops RTL and microarchitecture foundations through arithmetic units, pipelined datapaths, static timing analysis, clock and reset crossings, and FIFO design. Synchronous design comes first; asynchronous interfaces follow only after their assumptions and failure modes are established. Planned exercises connect simulation evidence with synthesis and timing reports, then introduce the stages of an automated physical implementation flow using an educational platform. The emphasis is disciplined digital design and interpretation of results. Transistor-level analog design, custom layout, foundry qualification, and professional physical-design signoff are outside scope. A final block-level project brings the design specification, constraints, verification results, and implementation observations together.

Learning objectives

• Translate a block specification into a documented datapath, controller, and interface contract.
• Compare arithmetic architectures and pipeline choices using latency, throughput, area, and timing evidence.
• Write basic timing constraints and explain setup, hold, skew, uncertainty, and slack reports.
• Select CDC and reset strategies appropriate to single-bit controls, pulses, and multibit transfers.
• Implement and verify synchronous FIFOs before designing a Gray-pointer asynchronous FIFO.
• Identify switching-activity and resource-sharing tradeoffs without treating rough estimates as signoff power.
• Run an introductory synthesis and implementation flow and explain its main inputs, artifacts, and limitations.
• Deliver a reproducible capstone with RTL, tests, constraints, measured results, and remaining assumptions.

Curriculum

Prerequisites

• Combinational and sequential logic, finite-state machines, and binary arithmetic.
• Synthesizable Verilog, module hierarchy, parameters, and correct blocking/nonblocking assignment use.
• Basic self-checking simulation, waveform inspection, and debugging.
• Comfort reading simple scripts and running command-line tools.

Course requirements

• A computer with a code editor, terminal, and waveform viewer.
• Access to a Verilog-capable simulator suitable for the planned RTL exercises.
• A working Yosys and OpenSTA installation or an equivalent synthesis and static-timing environment.
• For implementation exercises, an OpenROAD Flow Scripts environment and a compatible public educational platform; installation may require Linux, WSL, or containers.
• Git and enough local storage for tool builds, platform files, simulation traces, and implementation artifacts.

Who this course is for

• Learners who can already write and simulate synthesizable Verilog.
• Students developing stronger RTL design and microarchitecture judgment.
• Engineers seeking an introductory bridge from RTL behavior to timing and implementation reports.

Practice projects

Planned exercises for applying the syllabus.

1. Pipelined arithmetic block

   Planned exercise: specify a fixed-width multiply-accumulate datapath, compare iterative and pipelined versions, verify arithmetic corner cases, and report latency, throughput, and synthesized timing/area tradeoffs.

2. Dual-clock streaming buffer

   Planned exercise: build and test a synchronous FIFO, extend it to a power-of-two asynchronous FIFO with Gray-coded pointer crossings, and document reset behavior, occupancy boundaries, and CDC assumptions.

3. Constrained RTL implementation capstone

   Planned exercise: integrate a small streaming datapath and controller, create clock and I/O constraints, run synthesis and an introductory physical flow, and explain the reports and unresolved limitations.

Curriculum references

• MIT 6.375 Complex Digital Systems: course handouts

  University reference for combinational/sequential design, folded/pipelined circuits, synthesis, and progressive labs; its BSV-based implementation is not presented as a Verilog curriculum.

• AMD UG949: Constraining Clock Domain Crossings

  Supports reviewing clock relationships and crossing constraints; FPGA-specific guidance requires adaptation for ASIC examples.

• AMD UG949: Synchronous Reset vs. Asynchronous Reset

  Reset architecture and release considerations; device-specific recommendations are identified as such.

• OpenSTA maintained repository

  Primary documentation for gate-level timing analysis inputs and constraints.

• YosysHQ: Synthesis in detail

  Primary synthesis reference for processes, FSMs, memory handling, optimizations, and technology mapping.

• OpenROAD Flow Scripts user guide

  Defines the roles of Yosys, OpenROAD, and KLayout in the example automated implementation flow.

• OpenROAD Flow Scripts variables

  Supports public platform access, reproducible configuration, and introductory PPA observations.

Course availability

The research-informed outline describes the planned learning sequence. Enrolment, teaching media, dates and fees remain subject to confirmation.

Programme questions