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Courses Advanced design and verification

Advanced Digital IC

Move from working Verilog modules to digital blocks whose architecture, timing, interfaces, and implementation tradeoffs can be explained and measured.

12 sectionsSelf-paced learning

About this course

Move from working Verilog modules to digital blocks whose architecture, timing, interfaces, and implementation tradeoffs can be explained and measured. This course develops RTL and microarchitecture foundations through arithmetic units, pipelined datapaths, static timing analysis, clock and reset crossings, and FIFO design. Synchronous design comes first; asynchronous interfaces follow only after their assumptions and failure modes are established. Planned exercises connect simulation evidence with synthesis and timing reports, then introduce the stages of an automated physical implementation flow using an educational platform. The emphasis is disciplined digital design and interpretation of results. Transistor-level analog design, custom layout, foundry qualification, and professional physical-design signoff are outside scope. A final block-level project brings the design specification, constraints, verification results, and implementation observations together.

Where to start

Build the knowledge in these courses first, or bring equivalent practical experience:

What you’ll learn

  • Translate a block specification into a documented datapath, controller, and interface contract.
  • Compare arithmetic architectures and pipeline choices using latency, throughput, area, and timing evidence.
  • Write basic timing constraints and explain setup, hold, skew, uncertainty, and slack reports.
  • Select CDC and reset strategies appropriate to single-bit controls, pulses, and multibit transfers.
  • Implement and verify synchronous FIFOs before designing a Gray-pointer asynchronous FIFO.
  • Identify switching-activity and resource-sharing tradeoffs without treating rough estimates as signoff power.
  • Run an introductory synthesis and implementation flow and explain its main inputs, artifacts, and limitations.
  • Deliver a reproducible capstone with RTL, tests, constraints, measured results, and remaining assumptions.

Course syllabus

12 sections · 63 topics

01. Design contracts and synchronous RTL review5 topics
  1. Define functional behavior, clocking, reset polarity, and cycle-level interface expectations.
  2. Partition a design into datapath, control, state, and storage.
  3. Review latch avoidance, complete assignments, and deterministic sequential coding.
  4. Resolve width, signedness, overflow, and parameter elaboration corner cases.
  5. Build a small reference model and establish repeatable simulation checks.
02. Synchronous timing and design constraints5 topics
  1. Trace register-to-register, input-to-register, and register-to-output paths.
  2. Relate setup, hold, clock-to-Q, and combinational delay to timing feasibility.
  3. Distinguish latency, initiation interval, throughput, and target clock period.
  4. Introduce primary clocks, I/O timing budgets, clock uncertainty, and external interface assumptions.
  5. Separate related-clock paths from asynchronous crossings before adding timing exceptions.
03. Arithmetic structures and datapath architecture5 topics
  1. Compare ripple and faster-adder structures at the architectural level.
  2. Implement multiplication, accumulation, shifting, and selection with explicit widths.
  3. Define fixed-point representation, rounding, truncation, saturation, and overflow policy.
  4. Compare shared iterative resources with parallel arithmetic hardware.
  5. Verify signed limits, carry behavior, and parameter-dependent corner cases.
04. Pipelining and controlled data movement5 topics
  1. Choose pipeline cuts from combinational depth and cycle-level requirements.
  2. Align data, valid bits, tags, and control through pipeline stages.
  3. Implement ready/valid transfers and handle stalls without losing transactions.
  4. Explain bubbles, backpressure, dependency hazards, and pipeline flushing.
  5. Measure throughput and latency while checking reset and stalled-output behavior.
05. Static timing analysis and exception discipline5 topics
  1. Read netlist, Liberty timing libraries, and SDC inputs in an introductory STA flow.
  2. Interpret launch/capture paths, arrival time, required time, and slack.
  3. Evaluate setup and hold separately and explain skew and uncertainty effects.
  4. Diagnose unconstrained endpoints and incorrect I/O timing assumptions.
  5. Apply false-path or multicycle exceptions only with documented functional justification and matching hold intent.
06. Clock-domain crossings and reset release6 topics
  1. Explain metastability, synchronizer settling time, and why RTL simulation cannot prove CDC safety.
  2. Use a multistage synchronizer for an appropriately stable single-bit level.
  3. Compare pulse stretching, toggle transfer, and request/acknowledge handshakes.
  4. Protect multibit coherence instead of independently synchronizing arbitrary bus bits.
  5. Plan per-domain reset assertion and synchronized release, including recovery/removal and reset-crossing concerns.
  6. Review CDC structure and constraints together: a timing exception does not repair unsafe logic.
07. Synchronous FIFO architecture and verification5 topics
  1. Define storage depth, read latency, and full/empty interface semantics.
  2. Implement pointers, occupancy tracking, and wraparound for a single clock.
  3. Specify simultaneous enqueue/dequeue behavior at empty and full boundaries.
  4. Check ordering, overflow prevention, underflow prevention, and reset recovery.
  5. Exercise sustained traffic, burst traffic, and backpressure with a reference queue.
08. Asynchronous FIFO design6 topics
  1. Separate write-domain and read-domain state in a power-of-two-depth FIFO.
  2. Convert binary pointers to Gray code and synchronize pointers across domains.
  3. Derive full and empty conditions using synchronized remote pointers.
  4. Explain conservative flag latency and why cross-domain occupancy is not instantaneous.
  5. Review pointer-bus skew/maximum-delay requirements appropriate to the target implementation.
  6. Test independent clock ratios, pointer wraparound, boundary traffic, and coordinated reset assumptions.
09. Power, performance, and area tradeoffs6 topics
  1. Relate dynamic activity, capacitance, voltage, frequency, and leakage qualitatively.
  2. Compare resource sharing, operand isolation, pipeline depth, and unnecessary switching.
  3. Use clock enables for RTL exercises and explain technology-specific integrated clock gating.
  4. Recognize why combinational clock gating can create unsafe clock behavior.
  5. Compare area and timing under fixed constraints and state the limits of power estimates.
  6. Introduce power domains, isolation, and retention as concepts requiring additional power-intent and verification flows.
10. Synthesis and technology mapping5 topics
  1. Elaborate parameterized RTL and inspect inferred registers, multiplexers, arithmetic, and memories.
  2. Follow process lowering, optimization, and mapping into a selected cell library.
  3. Read warnings for latches, unresolved modules, width mismatches, and unsupported constructs.
  4. Compare mapped statistics and timing against the original architectural goals.
  5. Re-run functional checks after RTL optimization and preserve scripts and tool versions.
11. Introductory physical implementation flow5 topics
  1. Identify roles of Liberty, LEF, technology data, constraints, and the selected educational platform.
  2. Follow floorplanning, placement, clock-tree synthesis, routing, and parasitic-aware timing stages.
  3. Observe how utilization, congestion, buffering, and interconnect affect results.
  4. Compare pre-layout and post-route timing while distinguishing estimated and extracted effects.
  5. Inspect generated artifacts and distinguish educational checks from qualified signoff.
12. Integrated digital block capstone5 topics
  1. Write an implementable block specification and measurable acceptance conditions.
  2. Integrate arithmetic, control, buffering, reset, and timing assumptions.
  3. Run directed and randomized self-checking tests for boundary and sustained-traffic behavior.
  4. Collect synthesis, timing, and introductory implementation results using versioned scripts.
  5. Present architecture tradeoffs, CDC/reset review, known limitations, and reproducibility instructions.

Course requirements

  • A computer with a code editor, terminal, and waveform viewer.
  • Access to a Verilog-capable simulator suitable for the planned RTL exercises.
  • A working Yosys and OpenSTA installation or an equivalent synthesis and static-timing environment.
  • For implementation exercises, an OpenROAD Flow Scripts environment and a compatible public educational platform; installation may require Linux, WSL, or containers.
  • Git and enough local storage for tool builds, platform files, simulation traces, and implementation artifacts.

Prerequisites

  • Combinational and sequential logic, finite-state machines, and binary arithmetic.
  • Synthesizable Verilog, module hierarchy, parameters, and correct blocking/nonblocking assignment use.
  • Basic self-checking simulation, waveform inspection, and debugging.
  • Comfort reading simple scripts and running command-line tools.

Who this course is for

  • Learners who can already write and simulate synthesizable Verilog.
  • Students developing stronger RTL design and microarchitecture judgment.
  • Engineers seeking an introductory bridge from RTL behavior to timing and implementation reports.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Pipelined arithmetic block

    Planned exercise: specify a fixed-width multiply-accumulate datapath, compare iterative and pipelined versions, verify arithmetic corner cases, and report latency, throughput, and synthesized timing/area tradeoffs.

  2. Dual-clock streaming buffer

    Planned exercise: build and test a synchronous FIFO, extend it to a power-of-two asynchronous FIFO with Gray-coded pointer crossings, and document reset behavior, occupancy boundaries, and CDC assumptions.

  3. Constrained RTL implementation capstone

    Planned exercise: integrate a small streaming datapath and controller, create clock and I/O constraints, run synthesis and an introductory physical flow, and explain the reports and unresolved limitations.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

Course outline and pricing are subject to confirmation before enrolment opens.