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UVM

Build a reusable SystemVerilog verification environment by understanding each UVM mechanism before combining it with the next.

12 sectionsSelf-paced learning

About this course

Build a reusable SystemVerilog verification environment by understanding each UVM mechanism before combining it with the next. The course starts with objects, components, phases, and transaction models, then develops sequences, a correctly synchronized driver, passive monitoring, agents, and independent checking. Configuration and factory overrides are introduced after the basic data path is visible, making reuse decisions easier to debug. Later sections coordinate multiple interfaces, handle reset, connect a register model, and integrate assertions and functional coverage. Planned exercises culminate in a reproducible regression with failure triage and a documented coverage review. Advanced SystemVerilog knowledge is required; prior project work is useful but optional. The reference basis is IEEE 1800.2-2020 and Accellera implementation documentation, with explicit attention to simulator compatibility and differences from older UVM examples.

Where to start

Build the knowledge in these courses first, or bring equivalent practical experience:

What you’ll learn

  • Construct a UVM environment with clear responsibilities for tests, environments, agents, drivers, monitors, and scoreboards.
  • Model transactions and generate constrained stimulus using reusable sequences.
  • Implement the sequencer-driver handshake without deadlocks or premature transaction completion.
  • Connect analysis components and compare observed DUT behavior with an independent model.
  • Configure virtual interfaces and agent behavior through typed configuration objects.
  • Use factory overrides and coordinated sequences to vary tests without duplicating the environment.
  • Integrate a register model with adapters, prediction, and register access checks.
  • Use assertions, functional coverage, reproducible regressions, and debug evidence to assess verification completeness.

Course syllabus

12 sections · 69 topics

01. UVM architecture, objects, components, and phases6 topics
  1. Map a verification plan to stimulus, observation, checking, and coverage responsibilities.
  2. Distinguish uvm_object lifetime from hierarchical uvm_component lifetime.
  3. Build a minimal test, environment, and top module with explicit package dependencies.
  4. Follow build, connect, end-of-elaboration, run, and reporting responsibilities.
  5. Introduce reporting, objections, and deterministic end-of-test ownership.
  6. Record the selected library version and distinguish IEEE 1800.2 APIs from legacy examples.
02. Transactions and reusable sequences5 topics
  1. Define sequence items with protocol fields, legal constraints, and readable printing.
  2. Implement copy and compare behavior and reason about shallow versus deep object copying.
  3. Separate protocol legality from test-specific scenario constraints.
  4. Write directed and randomized sequences using explicit item creation and randomization checks.
  5. Use sequence parameters and composition to express boundary and stress scenarios.
03. Sequencer-driver handshake and pin-level execution6 topics
  1. Connect a typed sequencer and driver through the sequence-item interface.
  2. Implement get_next_item/item_done ordering and define when a transfer is complete.
  3. Drive clocked pins through an interface BFM using established sampling and driving conventions.
  4. Handle backpressure, wait states, and response timing without dropping or duplicating items.
  5. Return responses with correct transaction identity when the protocol requires them.
  6. Diagnose blocked sequences, missing completion calls, and shutdown races.
04. Passive monitors and reusable agents5 topics
  1. Reconstruct accepted transactions from interface activity independently of the driver.
  2. Handle reset and incomplete transfers without publishing misleading observations.
  3. Package monitor, driver, and sequencer into a protocol-specific agent.
  4. Support active and passive modes with clear ownership of interface driving.
  5. Publish fresh or safely copied transaction objects and test monitor correctness.
05. TLM analysis and independent checking6 topics
  1. Connect analysis ports, exports, subscribers, and analysis FIFOs.
  2. Explain nonblocking analysis writes and move time-consuming work into suitable processes.
  3. Separate prediction from comparison using an independent behavioral model.
  4. Check ordering, payload, responses, and missing or unexpected transactions.
  5. Use queues or identifiers to handle latency and supported out-of-order behavior.
  6. Drain pending checks before ending the test and report meaningful mismatch context.
06. Configuration and virtual interface binding5 topics
  1. Pass a virtual interface from the top module into the UVM environment.
  2. Use typed configuration objects for agent modes, handles, and protocol settings.
  3. Set and get configuration entries with deliberate hierarchy scope.
  4. Diagnose missing configuration, type mismatches, and excessively broad wildcards.
  5. Distribute configuration to sequences through explicit handles and well-defined ownership.
07. Factory creation and controlled overrides6 topics
  1. Register relevant object and component types and create them through the factory.
  2. Distinguish type overrides from instance overrides.
  3. Apply overrides before the affected objects or components are created.
  4. Replace a transaction, sequence, or component to inject a focused behavior change.
  5. Inspect effective factory settings and explain interactions with configuration.
  6. Keep customization readable rather than hiding behavior behind excessive macros.
08. Coordinated sequences, reset, and end-of-test control6 topics
  1. Coordinate child sequences across existing agent sequencers using explicit handles.
  2. Separate scenario coordination from protocol-specific transaction generation.
  3. Introduce sequencer arbitration and use exclusive access only when justified.
  4. Define how reset interrupts drivers, monitors, scoreboards, and outstanding transactions.
  5. Control objections, watchdog timeouts, and drain conditions from a clear owner.
  6. Test reset during traffic and restart scenarios with reproducible outcomes.
09. Register abstraction layer foundations6 topics
  1. Model fields, access policies, registers, blocks, and address maps.
  2. Distinguish desired values, mirrored values, and observed hardware state.
  3. Translate register operations through a bus adapter.
  4. Connect prediction and choose an explicit auto-prediction or monitor-based strategy.
  5. Exercise frontdoor access and explain backdoor access assumptions and limits.
  6. Check reset values, read/write behavior, side effects, and appropriate built-in sequences.
10. Assertions, coverage, and verification intent6 topics
  1. Reuse protocol assertions at the interface or bind layer with correct reset disabling.
  2. Define coverage points from planned behaviors instead of merely mirroring randomized fields.
  3. Sample coverage on observed accepted transfers and meaningful outcomes.
  4. Add crosses for boundary, mode, response, and reset scenarios with controlled size.
  5. Distinguish code coverage, functional coverage, assertions, and scoreboard evidence.
  6. Investigate uncovered requirements and document justified unreachable bins without claiming proof from a percentage.
11. Regressions and evidence-based debug6 topics
  1. Launch tests with recorded seeds, tool versions, library settings, and configuration.
  2. Classify compile failures, testbench errors, DUT mismatches, assertion failures, and timeouts.
  3. Reproduce a single failure and reduce stimulus before collecting deeper traces.
  4. Use verbosity, transaction identifiers, hierarchy inspection, and waveform correlation.
  5. Merge compatible coverage results and inspect gaps against the verification plan.
  6. Define pass criteria and distinguish passing tests from complete verification.
12. Integrated UVM capstone and reuse review6 topics
  1. Translate a small block specification into a prioritized verification plan.
  2. Integrate reusable agents, independent checking, coordinated stimulus, and register access where applicable.
  3. Run directed boundary tests before broad constrained-random regressions.
  4. Inject a known defect to check that monitors and checkers detect the intended failure.
  5. Review coverage holes, reset behavior, pending transactions, and regression stability.
  6. Deliver source, compile/run instructions, seeds, evidence, and a concise limitations report.

Course requirements

  • Access to a simulator with the SystemVerilog class, constrained-random, coverage, assertion, and UVM features needed by the exercises.
  • A compatible UVM library and documented compile/run setup; use the simulator-supported or validated Accellera implementation.
  • A code editor, terminal, waveform/log viewer, and a way to preserve test names and random seeds.
  • Git and a scripting environment for launching and collecting regression results.
  • Tool-specific coverage viewing or reporting access for coverage exercises; feature availability and licenses must be checked.

Prerequisites

  • SystemVerilog classes, inheritance, polymorphism, parameterized types, and object handles.
  • Constrained randomization, queues, mailboxes, events, and concurrent processes.
  • Interfaces, virtual interfaces, clocking blocks, assertions, and functional coverage fundamentals.
  • Self-checking RTL testbench experience; the Projects course is recommended practice rather than a required dependency.

Who this course is for

  • Learners comfortable with advanced SystemVerilog classes, interfaces, randomization, and coverage.
  • Verification engineers moving from custom class-based testbenches to reusable UVM environments.
  • RTL designers who want to understand block-level verification architecture and evidence.

Practice projects

Apply the topics in sequence through these planned exercises.

  1. Reusable FIFO verification agent

    Planned exercise: create transactions, sequences, a driver, and an independent monitor for a FIFO interface, then connect a reference queue and boundary-focused coverage.

  2. Register-mapped peripheral environment

    Planned exercise: verify a small register-mapped peripheral using a reusable bus agent, register model, adapter, prediction, access-policy checks, and reset tests.

  3. Coverage-guided verification capstone

    Planned exercise: combine coordinated traffic, reset scenarios, assertions, scoreboarding, and seeded regressions; document reproduced failures, coverage gaps, and justified exclusions.

Curriculum references

Primary documentation and teaching resources that inform this learning sequence.

Course outline and pricing are subject to confirmation before enrolment opens.