Understanding a D flip-flop, edge by edge

A positive-edge-triggered D flip-flop stores one bit. At a rising clock edge, it samples its D input; its Q output then reflects that captured value. Between sampling edges, Q retains its value, assuming no other control such as an asynchronous reset changes it.

That short description contains three separate ideas: the data being sampled, the event that samples it, and the value retained afterward. Reading a timing diagram becomes much easier when you follow those ideas one at a time instead of treating every transition as an instruction to change Q.

Name the signals and assumptions

We will call the input D, the clock clk, and the stored output Q. A rising edge is a transition of clk from 0 to 1. For this idealized example, assume Q starts at 0, all data transitions occur safely away from sampling edges, and no reset or preset is asserted during the sequence.

The starting value is an assumption for the example. A generic flip-flop is not guaranteed to power up at 0. Real designs establish required initial state through device-specific reset behavior or another valid initialization mechanism. Always state that mechanism when it matters to the behavior you are checking.

We will ignore propagation delay in the drawn sequence so that the sampling rule is easy to see. In actual hardware, Q changes after a clock-to-output delay rather than at exactly the same physical instant as the edge.

Read three rising edges

Let the first rising edge occur at time 1, the next at time 3, and the third at time 5. These are illustrative time coordinates, not nanoseconds or a claim about a particular device's speed. Suppose D is 1, 0 and 1 respectively at those edges.

At the first edge, copy D into the stored state: Q becomes 1. If D later falls to 0 before the next rising edge, Q still holds 1 during that interval. At time 3, the new D value is sampled and Q becomes 0. The third edge repeats the operation with D = 1.

Try drawing Q yourself on blank paper. Mark only the rising edges first, write the sampled D value above each one, and then connect the Q levels between them. This method prevents the common mistake of copying every D transition straight onto Q.

What happens while the clock is high?

A positive-edge-triggered flip-flop does not keep accepting new values simply because clk remains high. The transition into the high level is the sampling event in this model. Changing D midway through the high interval does not immediately update Q.

A falling edge also does not sample D in this positive-edge example. A negative-edge-triggered device follows a different convention. Check the symbol and specification before deciding which transitions matter; the word flip-flop alone does not tell you the active edge.

The following pseudocode is a compact reminder of the model. It is not executable HDL and does not model analog timing or reset controls.

initial assumption: Q = 0
on each rising edge of clk:
  Q becomes the sampled value of D
between those edges:
  Q holds its stored value

A latch follows a different rule

An active-high transparent D latch allows Q to follow D while its enable is high. When enable becomes low, it retains the captured level. A flip-flop instead samples around a specified edge. Both store a bit, but the intervals during which input changes can affect the stored result differ.

This distinction matters when reviewing a waveform. If Q follows several D transitions during one active interval, that behavior fits a transparent latch model, not the simple edge-triggered model used above. Do not use latch and flip-flop as interchangeable names when describing timing behavior.

Respect the sampling window

Real devices require D to be stable for specified setup and hold intervals around the active edge. If those requirements are violated, the captured value may not behave as the ideal diagram predicts; metastability is possible. A truth table cannot replace these timing requirements.

Likewise, an asynchronous clear or preset can affect Q independently of a normal sampling edge. The TI part listed below has such controls. Our example deliberately keeps them inactive. When moving from this teaching model to a real component, consult its complete function table and timing specifications, including restrictions on control combinations.

Try an edge-by-edge exercise

Assume Q initially equals 0. D becomes 1, but no rising edge occurs yet. Then a rising edge occurs with D still 1. D falls to 0 while clk remains high. What is Q after each of these three events?

Answer: 0, then 1, then 1. The first event changes only the input. The second samples that input. The third leaves the stored value unchanged. Q would become 0 at a later rising edge if D remained 0 and the timing requirements were satisfied. That separation between input change and sampling event is the central idea to keep.