An SR latch stores one bit using set and reset controls. For a NOR-based active-high latch, S = 1 sets Q, R = 1 resets Q, and S = R = 0 holds the prior state. A gated SR latch permits these actions only while its enable is active.
Worked example
Starting with Q = 0, apply S = 1 and R = 0 to make Q = 1. Return both inputs to zero: Q remains one. Later apply S = 0 and R = 1 to clear it. A gated version ignores inactive requests while its gate is disabled.
What to watch for
For the NOR latch, simultaneous S = R = 1 is the forbidden operating combination. NAND-based latches use active-low controls and a different forbidden combination.
Try it yourself
What happens to a NOR SR latch when S and R are both zero?
Answer: It holds its previous valid state. Zero here means neither set nor reset is requested.
How to study this topic
Write the old state, input values and next state in separate columns. Mark the active clock edge or enable interval. This prevents a stored value from being confused with an input that is merely waiting to be captured.
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Digital Electronics