Propagation delay is the time between a relevant input transition and the corresponding output transition, measured at defined voltage reference points. Power and delay tradeoffs depend on technology, supply, frequency and load. CMOS dynamic switching power is commonly approximated by activity × capacitance × voltage squared × frequency.
Worked example
If two serial gate stages each have an illustrative worst-case delay of 3 ns, their simple path estimate is 6 ns before considering wiring and load differences. For the same capacitance and activity, doubling switching frequency approximately doubles dynamic switching power.
What to watch for
Typical delay is not a guaranteed worst case. The power formula omits leakage and other effects, and increasing voltage changes both power and device operating conditions.
Try it yourself
How does halving capacitance affect the dynamic-power estimate if all other factors stay fixed?
Answer: It halves the estimate because capacitance appears as a linear factor.
How to study this topic
Use the numerical values here as teaching examples. For a physical design, consult the actual component data sheet at the intended supply, load and temperature. Logical equivalence alone does not establish electrical compatibility.
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Digital Electronics