A CMOS inverter uses a pull-up PMOS transistor and a pull-down NMOS transistor. In its ideal settled states, one connects the output toward the supply while the other is off. More complex complementary transistor networks implement gates such as NAND and NOR.
Worked example
With a low inverter input, the PMOS is on and the NMOS is off, so the output goes high. With a high input, the roles reverse and the output goes low. A CMOS NAND uses series NMOS devices in its pull-down network and parallel PMOS devices in its pull-up network.
What to watch for
Real CMOS consumes leakage power in settled states and switching power during transitions. Both transistors can briefly conduct while the input passes through intermediate voltages.
Try it yourself
For a two-input CMOS NAND, when does the pull-down path conduct fully?
Answer: When both inputs are high, turning on both series NMOS devices. The resulting output is low.
How to study this topic
Use the numerical values here as teaching examples. For a physical design, consult the actual component data sheet at the intended supply, load and temperature. Logical equivalence alone does not establish electrical compatibility.
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Digital Electronics