Skip to content

Home Courses Blog About Contact Login

Home Courses Blog About Contact Login

Explore Chiprion

Home Courses Blog About Contact Login

Advanced Digital IC overview

Advanced Digital IC

Browse sections and subtopics. Article links appear where published.

Browse Advanced Digital IC topics

01 · Digital IC Design Foundations

1.1 · Abstraction from devices to systemsNo article yet
1.2 · ASIC and FPGA design flowsNo article yet
1.3 · Technology scaling and design tradeoffsNo article yet
1.4 · Power, performance and area metricsNo article yet
1.5 · Design specifications and constraintsNo article yet

02 · MOS Devices and CMOS Inverters

2.1 · MOS switching and device modelsNo article yet
2.2 · CMOS inverter transfer characteristicsNo article yet
2.3 · Noise margins and switching thresholdsNo article yet
2.4 · Parasitic capacitanceNo article yet
2.5 · Inverter delay and sizingNo article yet
2.6 · Process, voltage and temperature cornersNo article yet

03 · CMOS Logic Styles

3.1 · Static CMOS gate constructionNo article yet
3.2 · Complex gates and transistor sizingNo article yet
3.3 · Ratioed logicNo article yet
3.4 · Pass-transistor and transmission-gate logicNo article yet
3.5 · Dynamic and domino logicNo article yet
3.6 · Charge sharing and leakageNo article yet
3.7 · Logic-style tradeoffsNo article yet

04 · Delay and Interconnect

4.1 · RC delay and Elmore modelsNo article yet
4.2 · Logical effort and electrical effortNo article yet
4.3 · Buffer chains and repeater insertionNo article yet
4.4 · Wire resistance and capacitanceNo article yet
4.5 · Coupling and crosstalkNo article yet
4.6 · Interconnect-aware optimizationNo article yet

05 · Sequential Circuit Design

5.1 · Static latches and registersNo article yet
5.2 · Dynamic latches and registersNo article yet
5.3 · Pulse-triggered storageNo article yet
5.4 · Setup, hold and clock-to-Q characterizationNo article yet
5.5 · Time borrowingNo article yet
5.6 · Metastability and synchronizer designNo article yet

06 · Clocking and Static Timing Analysis

6.1 · Clock distribution and clock treesNo article yet
6.2 · Skew, jitter and uncertaintyNo article yet
6.3 · Timing paths and constraintsNo article yet
6.4 · Setup and hold timing closureNo article yet
6.5 · Generated clocksNo article yet
6.6 · False paths and multicycle pathsNo article yet
6.7 · Timing corners and variationNo article yet
6.8 · Clock-domain and reset-domain crossingsNo article yet

07 · Arithmetic and Datapath Architecture

7.1 · Fast adder architecturesNo article yet
7.2 · Carry-save arithmeticNo article yet
7.3 · Booth encoding and multiplier treesNo article yet
7.4 · Shifters and arithmetic unitsNo article yet
7.5 · Pipelining and retimingNo article yet
7.6 · Throughput versus latencyNo article yet
7.7 · Resource sharing and datapath controlNo article yet

08 · Low-Power Design

8.1 · Switching, short-circuit and leakage powerNo article yet
8.2 · Activity and capacitance reductionNo article yet
8.3 · Clock gatingNo article yet
8.4 · Power gating and isolationNo article yet
8.5 · Retention and level shiftersNo article yet
8.6 · Voltage and frequency scalingNo article yet
8.7 · Power intent and UPF conceptsNo article yet

09 · Memory Circuit Design

9.1 · SRAM cells and stabilityNo article yet
9.2 · Read and write pathsNo article yet
9.3 · Sense amplifiers and prechargeNo article yet
9.4 · DRAM cells and refreshNo article yet
9.5 · ROM and programmable arraysNo article yet
9.6 · Memory organization and peripheral circuitsNo article yet
9.7 · Memory timing and power tradeoffsNo article yet

10 · Synthesis and Physical Implementation

10.1 · RTL synthesis and technology mappingNo article yet
10.2 · Standard-cell libraries and characterizationNo article yet
10.3 · Floorplanning and power planningNo article yet
10.4 · Placement and congestionNo article yet
10.5 · Clock-tree synthesisNo article yet
10.6 · Routing and parasitic extractionNo article yet
10.7 · Design-rule and layout-versus-schematic checksNo article yet
10.8 · Timing and power signoffNo article yet

11 · Testability and Reliability

11.1 · Fault models and test coverageNo article yet
11.2 · Scan chains and scan insertionNo article yet
11.3 · ATPG and test compressionNo article yet
11.4 · Logic and memory built-in self-testNo article yet
11.5 · Equivalence checkingNo article yet
11.6 · IR drop and electromigrationNo article yet
11.7 · Variation, aging and robustnessNo article yet

12 · System Integration and Design Studies

12.1 · Controller and datapath partitioningNo article yet
12.2 · On-chip buses and arbitrationNo article yet
12.3 · Asynchronous FIFO designNo article yet
12.4 · Pipeline and memory integrationNo article yet
12.5 · Design-space explorationNo article yet
12.6 · Implementation results and debuggingNo article yet

Testability and Reliability

Scan chains and scan insertion

No article has been published for this subtopic yet. Browse the topic index to find available articles.

Precision Training for Chip Engineers

Digital design and verification.
For anyone who wants to enter the VLSI and chip industry.

Explore

Home Courses Blog About Chiprion Contact

Stay connected

Emailsupport@chiprion.com Call Chiprion+91 83049 05706 WhatsAppTalk to Chiprion

LinkedIn Instagram

Headquarters: Hyderabad, Telangana, India

© 2026 Chiprion

Privacy Policy Terms and Conditions Refund Policy