A synchronous sequential circuit updates state according to a shared clock and defined sampling rules. An asynchronous sequential circuit can change state directly in response to input transitions without that common clock. Both retain state, but their timing assumptions and verification methods differ substantially.
Worked example
In a synchronous controller, changing a request between edges normally affects state at the next sampling edge. In an asynchronous controller, the request may begin a state transition immediately, followed by further settling according to internal delays and the handshake design.
What to watch for
Asynchronous design is not simply synchronous logic with the clock removed. Feedback, hazards, input sequencing and completion detection need deliberate treatment.
Try it yourself
Does an asynchronous input make an otherwise clocked controller an asynchronous sequential circuit?
Answer: No. The controller can remain synchronous while using a suitable crossing interface for that input.
How to study this topic
Draw the launch edge, capture edge and data transition on one timeline. Use guaranteed limits for real timing checks. Identify the clock domain and signal type before choosing a synchronizer or crossing protocol.
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Digital Electronics