Combinational and sequential logic — where state changes the answer

Combinational logic calculates an output from its current inputs. Sequential logic includes stored state, so its behavior can depend on information retained from earlier events. The most useful question is therefore: “Can I determine the result from the present inputs alone, once the circuit has settled?”

This distinction helps when reading both diagrams and hardware descriptions. A box labeled logic could describe either kind of circuit. To understand what it does, look for the input relationships, the storage elements, and the rules that change any stored values.

A rule with no remembered history

Take a permission signal defined as request AND ready. If request is 1 and ready is 1, permission is 1. If either input is 0, permission is 0. It does not matter whether request was previously 0 for one second or one hour: the settled result follows the present combination.

Now imagine a two-input selector. Its select input chooses which data input appears at the output. The selected value might represent a number, a control bit or part of an instruction. The circuit is still combinational if its output is fully determined by the present data and select inputs. “Combinational” does not mean “only a single gate.”

For a concrete check, suppose input X is 0, input Y is 1, and select chooses Y. The output is 1. Change X to 1 while still selecting Y and the settled output stays 1. A complete specification would describe both select values and every relevant data combination.

Add a remembered request

Suppose a request lasts briefly, but a controller must remember that it happened until another event acknowledges it. A live request signal alone cannot provide that information after it returns to 0. Introduce a stored pending bit instead.

Here is an illustrative rule evaluated at each positive clock edge. Start with pending = 0. An acknowledge clears pending; otherwise a request sets it; otherwise it holds its previous value. The priority is explicit: if both acknowledge and request are 1 at the sampling edge, acknowledge wins in this example.

At each rising clock edge:
  if acknowledge = 1: next_pending = 0
  else if request = 1: next_pending = 1
  else: next_pending = pending

This pseudocode describes one chosen behavior, not a universal request protocol. The hold case is the important difference. When both external inputs are 0, pending can be either 0 or 1 depending on the stored state. The same current inputs can therefore accompany different outputs.

Follow the state across events

Compare edges 2 and 4. Their current request and acknowledge inputs are identical, but pending differs. The request captured at edge 1 explains the difference. A table of external inputs alone would lose that context; a state-transition description includes it.

When sketching such a circuit, draw the combinational next-state calculation separately from the storage. The current stored value feeds back into that calculation. This makes it easier to ask two distinct questions: what value should be stored next, and when should the storage accept it?

A clock is common, not the definition

Synchronous sequential circuits commonly use a shared clock to coordinate updates. However, stored state is the defining feature of sequential logic. A level-sensitive latch can store a bit without behaving like a positive-edge-triggered flip-flop, and asynchronous sequential circuits do not require a common clock.

For a transparent latch, an active enable allows the output to follow the data; when that enable becomes inactive, the latch retains a value. This is different from sampling only at a specified clock edge. When reading a symbol or description, identify which storage behavior is intended rather than assuming every memory element is a flip-flop.

Delay is not stored state

Real combinational circuits have propagation delay. Immediately after an input changes, the output may still show an earlier value or pass through a transient. That physical delay does not by itself turn the circuit into a sequential memory element. Its settled logical output still follows the current input combination.

Conversely, a sequential circuit's state is an intentional part of its behavior. A pending bit retains a request because the update rule tells it to hold, not merely because a gate has not finished responding. Mixing up these two explanations makes timing diagrams harder to interpret.

Check your understanding

Is a circuit that reports whether a four-bit number is zero combinational or sequential? What about a circuit that counts how many requests have occurred?

Answer: the zero detector can be combinational because the current four input bits determine the result. A request counter needs state to retain its count between events. Its exact design also needs an initial value, an update event, an overflow rule and any reset behavior. Naming those assumptions turns a broad idea into something precise enough to check.