An FSM implementation connects a state register to combinational next-state logic and output logic. Reset selects the initial state. At each active edge, the register captures the next-state value computed from the old state and current inputs. This separation makes the controller's cycle behavior easier to reason about.
Worked example
A two-state request tracker uses Q = 0 for IDLE and Q = 1 for BUSY. Let start move IDLE to BUSY and done move BUSY to IDLE. Define D = (NOT Q AND start) OR (Q AND NOT done). Reset clears Q to IDLE.
What to watch for
The equation defines which input matters in each state. If start and done can conflict, specify the intended behavior rather than assuming a software-style ordering.
Try it yourself
What happens with Q = 1 and done = 1 in this implementation?
Answer: D becomes zero, so the next active clock edge returns the machine to IDLE regardless of start.
How to study this topic
Begin with named states and a complete transition table. Then choose encodings and derive the logic. Trace inputs over several cycles, checking outputs as well as next states, including reset and unexpected encodings.
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